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8 Mbit LPC Flash
A Microchip Technology Company
SST49LF080A
Data Sheet
Toggle Bit
During the internal Program or Erase operation, any consecutive attempts to read D[6] will produce
alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is
completed, the toggling will stop.
Multiple Device Selection
Multiple LPC flash devices may be strapped to increase memory densities in a system. The four ID
pins, ID[3:0], allow up to 16 devices to be attached to the same bus by using different ID strapping in a
system. BIOS support, bus loading, or the attaching bridge may limit this number. The boot device
must have an ID of 0 (determined by ID[3:0]); subsequent devices use incremental numbering. Equal
density must be used with multiple devices.
When used as a boot device, ID[3:0] must be strapped as 0000; all subsequent devices should use a
sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). With the hardware strapping, ID informa-
tion is included in every LPC address memory cycle. The ID bits in the address field are inverse of the
hardware strapping. The address bits [A 24 :A 23 , A 21 :A 20 ] are used to select the device with proper IDs.
See Table 7 for IDs. The SST49LF080A will compare these bits with ID[3:0]’s strapping values. If there
is a mismatch, the device will ignore the remainder of the cycle.
Table 7: Multiple Device Selection Configuration
Hardware Strapping
Address Bits Decoding
Device #
0 (Boot device)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ID[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A 24
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
A 23
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
A 21
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A 20
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
T7.0 25026
?2011 Silicon Storage Technology, Inc.
14
DS25086A
11/11
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